Invention relates to design of integrated circuits and more particularly to a method for optimizing net lists using simultaneous placement optimization, logic function optimization and net buffering.
Prior art methods use a mathematical expression to provide an analytical solution for simultaneous placement of logic functions and logic optimization. The solution of such a mathematical expression would lie in the continuous domain. Furthermore, mapping this solution into a valid placement and a valid implementation of each logic function can lead to loss of optimality.
Therefore, there is a need for a method that will overcome the deficiencies found in the prior art.
Invention discloses a method for the design and fabrication of integrated circuits to optimize signal timing and circuit performance.
The method simultaneously obtains a placement of logic functions, mapping of logic functions onto library elements and buffering of nets connecting the logic functions to optimize signal timing. Logic functions may be moved between bins and or may be optimized to obtain the best cost. A best buffering solution is also computed for each logic function""s location and size.